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Espressif Systems /ESP32-S3 /SPI1 /CMD

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Interpret as CMD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FLASH_PE)FLASH_PE 0 (USR)USR 0 (FLASH_HPM)FLASH_HPM 0 (FLASH_RES)FLASH_RES 0 (FLASH_DP)FLASH_DP 0 (FLASH_CE)FLASH_CE 0 (FLASH_BE)FLASH_BE 0 (FLASH_SE)FLASH_SE 0 (FLASH_PP)FLASH_PP 0 (FLASH_WRSR)FLASH_WRSR 0 (FLASH_RDSR)FLASH_RDSR 0 (FLASH_RDID)FLASH_RDID 0 (FLASH_WRDI)FLASH_WRDI 0 (FLASH_WREN)FLASH_WREN 0 (FLASH_READ)FLASH_READ

Description

SPI1 memory command register

Fields

FLASH_PE

In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable.
USR

User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_HPM

Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_RES

This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_DP

Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_CE

Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_BE

Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_SE

Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_PP

Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
FLASH_WRSR

Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_RDSR

Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_RDID

Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
FLASH_WRDI

Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
FLASH_WREN

Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
FLASH_READ

Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data